In general, the invention relates to integrated circuit devices. In particular, the invention relates to buffer circuits that minimize offset variation.
Generally, programmable logic devices (PLD) and other types of integrated circuits require interface circuitry such as input and output buffers for amplifying and/or conditioning signals for detection or transmission. In the case of an input buffer, the circuit receives an input signal that has typically undergone degradation and attenuation as it has propagated through a transmission link. The function of an input buffer is therefore to amplify and recondition the received signal, and in some cases to provide frequency equalization, so that the receiver circuitry can properly resolve the incoming bits. In the case of an output buffer, the circuit is typically required to drive an output signal at the appropriate levels for a given transmission link.
In either case, signal offset variation in the buffer circuitry can contribute to operational error. For example, offset variation can cause a low voltage level (i.e., a binary 0) to be read as a high voltage level (i.e., a binary 1). Furthermore, any offset variation existing in the first stage of a typical multi-stage limiting amplifier in the analog front-end of a receiver is amplified by subsequent stages. Offset variation reduces the available timing margins needed to resolve incoming data bits. This can cause an increase in the bit error rate (BER) of the receiver circuit. This problem is further exacerbated by integrated circuits shrinking in size and operating at reduced voltage margins while concurrently supporting transmission standards with increasingly higher data rates.
One technique for reducing offset-related operational error in an integrated buffer circuit is to provide programmable logic that dynamically monitors and cancels signal offset in the buffer circuit via one or more feedback loops. This technique is described in detail in U.S. Pat. No. 7,321,259, which is hereby incorporated herein by reference in its entirety. While that method works well to provide offset cancellation/reduction, feedback circuitry can be complex. In addition, more can be done during the production of integrated circuits to reduce signal offset variation even in circuits already supporting that and other methods of offset cancellation/reduction.